The formation of various integrated circuit (IC) structures on a wafer often relies on lithographic processes, sometimes referred to as photolithography, or simply lithography. As is well known, lithographic processes can be used to transfer a pattern of a photomask (also referred to herein as a mask or a reticle) to a wafer.
For instance, patterns can be formed from a photoresist layer disposed on the wafer by passing radiation energy through a mask having an arrangement to image the desired pattern onto the photoresist layer. As a result, the pattern is transferred to the photoresist layer. In areas where the photoresist is sufficiently exposed and after a development cycle, the photoresist material can become soluble such that it can be removed to selectively expose an underlying layer (e.g., a semiconductor layer, a metal or metal containing layer, a dielectric layer, a hard mask layer, etc.). Portions of the photoresist layer not exposed to a threshold amount of radiation energy will not be removed and serve to protect the underlying layer during further processing of the wafer (e.g., etching exposed portions of the underlying layer, implanting ions into the wafer, etc.). Thereafter, the remaining portions of the photoresist layer can be removed. Although the above refers to a positive resist process, negative resist processes can also be utilized to pattern a photoresist layer.
There is a pervasive trend in the art of IC fabrication to increase the density with which various structures are arranged. For example, feature size, line width, and the separation between features and lines are becoming increasingly smaller. For example, nodes with a critical dimension of about 45 nanometers (nm) to about 65 nm have been proposed. In these sub-micron processes, yield is affected by factors such as mask pattern fidelity, optical proximity effects, and photoresist processing. Some of the more prevalent concerns include line end pullback, corner rounding and line-width variations. These concerns are largely dependent on local pattern density and topology.
Optical proximity correction (OPC) has been used to improve image fidelity for photolithographic applications. In general, current OPC techniques involve running a computer simulation that takes an initial data set having information relating to the desired pattern and manipulates the data set to arrive at a corrected data set in an attempt to compensate for the above-mentioned concerns. The photomask can then be made in accordance with the corrected data set. Briefly, the OPC process can be governed by a set of geometrical rules (e.g., “rule-based OPC” employing fixed rules for geometric manipulation of the data set), a set of modeling principles (e.g., “model-based OPC” employing predetermined behavior data to drive geometric manipulation of the data set) or a hybrid combination of rule-based OPC and model-based OPC.
The computer simulation can involve iteratively refining the data set using an edge placement error (EPE) value as a benchmark for the compensating process. In some OPC processes, the features and lines of the desired (or target) pattern are broken into edge fragments (or edge segments) and each edge fragment is associated with a simulation point (also referred to as a control point). The fragmented data set is manipulated based on the rules and/or models. For example, the edge fragments can be moved inward or outward. Then, a simulation can be run to determine predicted placement of the edges by simulated “imaging” of the manipulated pattern onto a wafer. The predicted edges are compared against their desired placement and, for a single point along each edge fragment such as the simulation point, a determination of how far the predicted edge placement deviates from the desired location is derived. If the predicted edge placement corresponds to the desired location, the edge placement error for that edge will be zero. As the predicted edge placement varies from the desired location, a positive or negative value in nanometers (or fractions thereof) can be derived. Determining EPE in this manner provides a one dimensional value for the offset between the desired edge (or segment thereof) and the predicted edge fragment placement.
Conventional OPC fragmentation schemes utilize corners of the target layout pattern as reference points for the segmentation of edges. FIG. 1 is a diagram that depicts a prior art OPC fragmentation scheme for a target layout pattern 102. A first corner 104 is utilized as the reference for the uppermost horizontal edge of target layout pattern 102. This simplified example shows five equidistant fragment lines 106 that are based on first corner 104 as a reference point. Similarly, a second corner 108 is used as the reference point for equidistant fragmentation lines 110 corresponding to the opposing edge, a third corner 112 is used as the reference point for equidistant fragmentation lines 114 corresponding to the lowermost horizontal edge of target layout pattern 102, and a fourth corner 116 is used as the reference point for equidistant fragmentation lines 118 corresponding to the opposing edge. The vertical edges of target layout pattern 102 are fragmented in a similar manner using horizontal fragment lines.
The fragmentation depicted in FIG. 1 results in 21 polygonal segments (bordered by dashed lines). Notably, some of the segments are relatively small and some are relatively large; this is because the segments are not consistently aligned across the overall geometry of target layout pattern 102. Such inconsistency can result in an unnecessarily large number of polygonal segments, which can lead to longer OPC processing times, longer mask writing times, and unreasonably large file sizes for the related mask writing data.